Bruce Jacob

Professor - 9

Bruce Jacob joined Florida Poly in the summer of 2021 as chair of the Electrical and Computer Engineering Department, coming from the University of Maryland, where he spent the previous 25 years as a professor.

He has been named a Fellow of IEEE “for contributions to computer memory design and analysis.” He currently designs computer-system architectures and computer memory-system architectures for both industry and government, national and international, focusing on highly efficient designs at the High-Performance Computing level, as well as at the high-performance embedded-systems level. For instance, he helped Micron design their new Hybrid Memory Cube DRAM architecture, redesigned Cray’s memory controller for their Black Widow memory system, helped Northrop Grumman design a system interconnect for their experimental ultra-low-power datacenter, designed a high-performance memory system for the 1024-core Teraflux chip funded by the European Commission, and he currently collaborates with researchers at the Department of Energy on the design of their next-generation supercomputers.

Recognized internationally as a leading expert on computer memory systems, Jacob founded the annual International Symposium on Memory Systems and is regularly invited to give keynote speeches and high-level briefings around the world on the topic of memory systems. He has been the keynote speaker at meetings including EMS, MCHPC, SAMOS, Multicore World, and Computing Frontiers. In 2007, he was one of 15 members of academia and industry invited to brief a National Academies panel on the then-current state of computing, resulting in the highly-cited NRC exascale report The Future of Computing Performance—Game Over or Next Level? In 2012, he was one of 20 members of academia and industry asked to brief the Secretary of Energy, Steven Chu, on the state of computing relative to the Department of Energy’s plans to achieve exascale-class computer performance. In 2016, he was one of a dozen members of academia and industry invited to participate with DOE in creating a roadmap for computer science and applied mathematics research at DOE in the coming decades. In 2020, he was one of four members of academia and two dozen members of industry and national labs invited to work with SRC, SIA, and DOE to develop a roadmap for memory devices and systems in the coming decade.

In addition to his academic credentials, Jacob has significant industry experience. Between college and graduate school, he worked in the start-up industry in Boston for two different telecommunications companies, serving as a software engineer at Boston Technology and then as the chief engineer and system architect at Priority Call Management. Both of these start-up companies were successful—in particular, Priority Call Management, for which Jacob designed and developed the product’s system-level architecture, its distributed middleware code, and its object-oriented applications framework, was purchased for $162 million in the late 1990s.

Jacob has written two textbooks on computer memory systems and over 80 articles on memory systems, computer design, embedded systems, operating system design, astrophysics, and algorithmic composition. His body of research has been cited over 7,200 times, with an h-index of 37. He holds a patent in memory-systems design and three patents in the circuit design of electric guitars—in 2009, the electric guitars were featured on Washington DC local television and radio stations; in articles appearing in The Washington Post, Los Angeles Times, and The Chronicle of Higher Education; on National Public Radio, Jacob and his graduate student were interviewed by Robert Siegel on All Things Considered on July 10, 2009.

  • Fellow, Institute of Electrical and Electronics Engineers, 2020 (effective 2021)
  • Award Fellowship Committee, ACM/IEEE CS George Michael Memorial HPC Award, 2018–2020
  • “Research Leader” (nee “Rainmaker”) University of Maryland, 2017/16/12/10/06/05/01
  • Keystone Professor, Clark School of Engineering, 2006
  • CAREER Award, National Science Foundation, 1999
  • Ph.D. in Computer Science and Engineering, The University of Michigan, 1997
  • M.S. in Computer Science and Engineering, The University of Michigan, 1995
  • A.B. in Mathematics (cum laude), Harvard University, 1988
  • Memory systems and devices
  • Operating systems
  • Distributed systems
  • Electric guitar design
  • Startup companies and entrepreneurship
  • Fellow, Institute of Electrical and Electronics Engineers (IEEE)
  • Founder, International Symposium on Memory Systems (published by ACM and IEEE)
  • Founder, Coil Guitars
  • Associate Editor, IEEE Computer Architecture Letters (CAL), 2007–2011
  • Associate Editor, ACM Transactions on Embedded Computing Systems (TECS), 2006–2009
  • B. Jacob, S. Ng, and D. Wang, with contributions by S. Rodriguez. Memory Systems: Cache, DRAM, Disk. ISBN 978-0123797513. Morgan Kaufmann: San Francisco CA, 2007. Citations 7/2021: 1021
  • P. Rosenfeld, E. Cooper-Balis, and B. Jacob. “DRAMsim2: A cycle-accurate memory-system simulator.” Computer Architecture Letters, vol. 10, no. 1, pp. 16–19. January 2011. Citations 7/2021: 959
  • D. Wang, B. Ganesh, N. Tuaycharoen, K. Baynes, A. Jaleel, and B. Jacob. “DRAMsim: A memory-system simulator.” SIGARCH Computer Architecture News, vol.33, no. 4, pp. 100–107. September 2005. Citations 7/2021: 391
  • A. Rodrigues, K. Hemmert, B. Barrett, C. Kersey, R. Oldfield, M. Weston, R. Risen, J. Cook, P.Rosenfeld, E. Cooper-Balls, and B. Jacob. “The Structural Simulation Toolkit.” ACM SIGMETRICS Performance Evaluation Review, vol. 38, no. 4, pp. 37–42. March 2011. Citations 7/2021: 300
  • V. Cuppu, B. Jacob, B. Davis, and T. Mudge. “A performance comparison of contemporary DRAM architectures.” In Proc. 26th Annual ACM/IEEE International Symposium on Computer Architecture (ISCA 1999), pp. 222–233. Atlanta GA, May 1999. Citations 7/2021: 290
  • C. Dirik and B. Jacob. “The performance of PC solid-state disks (SSDs) as a function of bandwidth, concurrency, device architecture, and system organization.” In Proc. 36th International Symposium on Computer Architecture (ISCA 2009), pp. 279–289. Austin TX, June 2009. Citations 7/2021: 270
  • M.-T. Chang, P. Rosenfeld, S.-L. Lu, and B. Jacob. “Technology comparison for Large Last-Level Caches (L3Cs): Low-leakage SRAM, low write-energy STT-RAM, and refresh-optimized eDRAM.” In Proc. 19th International Symposium on High Performance Computer Architecture (HPCA 2013), pp. 143–154. Shenzhen China, February 2013. Citations 7/2021: 257
  • A. Jaleel, R. S. Cohn, C.-K. Luk, and B. Jacob. “CMP$im: A Pin-based on-the-fly multi-core cache simulator.” In Proc. Fourth Annual Workshop on Modeling, Benchmarking and Simulation (MoBS 2008), pp. 28–36. Beijing China, June 2008. Citations 7/2021: 224
  • K. Albayraktaroglu, A. Jaleel, X. Wu, M. Franklin, B Jacob, C. Tseng, and D. Yeung. “BioBench: A benchmark suite of bioinformatics applications.” In Proc. 2005 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2005), pp. 2–9. Austin TX, March 2005. Citations 7/2021: 210
  • B. Jacob. “Composing with genetic algorithms.” In Proc. 1995 International Computer Music Conference (ICMC 1995), pp. 452–455. Banff Alberta, September 1995. Citations 7/2021: 192